Introduction
As defines by the IEEE 1588 standard, the slave sends to the master node a DELAY-REQUEST message at uniformly distributed time intervals. This message contains the timestamp measured by the slave clock when the message is sent.
A slave node receives periodically a SYNC message from the master node, which contains an estimate of the time when it was sent. When a SYNC message is received. The slave measures the time instant when it receives a SYNC message and it stores this value in memory.
Finally, after sending a DELAY-REQUEST message, the slave node receives from the master a DELAY-RESPONSE message, which contains a timestamp value. This timestamp corresponds to the time instant at which the DELAY-REQUEST message was received by the master.
The IEEE 1588 standard defines other kind of messages, useful for the additional mechanism necessary to support the reconfiguration of the network, for instance when nodes are added or deleted, when clock characteristics change or when connection topology changes. In these situations a new master could be determined.
The X-simulator considers only the SYNC, DELAY-REQUEST and DELAY-RESPONSE messages. The FOLLOW-UP messages have not been implemented since in the simulation environment they are not necessary. Neither the management messages have been implemented for the same reason.
Implementation
The slave module, illustrated in Fig. 1, is a compound module, having one input and one output.
It is composed by 5 simple modules.
- node module represents the core of the slave module since it implements the PTP synchronization protocol in order to synchronize its clock with the time reference. Furthermore, it may receive cyclic and acyclic messages in order to simulate a real node.
- The generation of cyclic - acyclic traffic is managed by the manager module. This module can be seen as an individual traffic source at application level.
- The clock module is the time reference for the slave node. It is used to model both the system clock and the timestamping mechanism.
- Finally, the bufferrx and buffertx nodes are realizations of the buffer module, that simulates the behaviour of a first-in first-out (FIFO) transmission queue.
The interactions between the internal modules of the slave module are described in the section related to the node module.
Since the slave module is a compound module, it has not a C++ code associated to it.