Program



Sunday, September 17
09:00-20:00Check-in & Reception (Via Frangipane, 6)
19:00-21:00Welcome Buffet (“Center Canteen” - Via Frangipane, 2)


Monday, September 18
07:30-08:45Breakfast (“Center Canteen”)
08:30-08:45Registration (“Fresco Room” - La Rocca, Via Frangipane, 6)
08:45-09:00Welcome
09:00-09:30Conditions for scalability: Memory capacity vs Network bandwidth
 Jose Moreira (IBM Thomas J. Watson Research Center)
09:30-10:00Exploiting non-volatile and high-bandwidth memory for HPC
 Dirk Pleiter (Jülich Supercomputing Center, Germany)
10:00-10:30Parallel memories: a feasible solution for bandwidth-limited applications?
 Ana Lucia Varbanescu (University of Amsterdam, Netherlands)
10:30-11:00Coffee
11:00-11:30An accelerator to aggregate key-value pairs for graph analytics using NAND flash storage
 Arvind, Sang-Woo Jun and Andy Wright (CSAIL, MIT, USA)
11:30-12:00E2MC: Entropy Encoding Based Memory Compression for GPUs
 Ben Juurlink (T.U. Berlin, Germany)
12:00-12:30Application autotuning for energy efficient heterogeneous HPC systems
 Cristina Silvano (Politecnico di Milano, Italy)
13:00-14:30Lunch (“Center Canteen”)
14:30-15:00Efficient Resource-Oblivious Multithreaded Algorithms
 Vijaya Ramachandran (University of Texas at Austin, USA)
15:00-15:30Matrix multiplication, a little faster
 Oded Schwartz (Hebrew University, Israel)
15:30-16:00Optimal On-Line Computation of Stack Distances for MIN and OPT
 Gianfranco Bilardi (University of Padova, Italy)
16:00-16:30Diversity maximization in MapReduce and Streaming
 Matteo Ceccarello (University of Padova, Italy)
16:30-17:00Coffee
17:00-18:30Discussion Session I: Algorithmic models for memory and storage
 Coordinators: V. Ramachandran, O. Schwartz
19:30-22:00Dinner, La divina bistecca, Via dei Santi, 3, 47032 Bertinoro FC, Italy, (+39 0543 445860).


Tuesday, September 19
07:30-08:45Breakfast (“Center Canteen”)
09:00-09:30Cognifying the HPC Ecosystem for Sustainability and Manageability
 Ozalp Babaoglu (University of Bologna, Italy)
09:30-10:00Continuum Computer Architecture for High Performance Computing
 Thomas Sterling (School of Informatics, Computing, and Engineering Indiana University, USA)
10:00-10:30A sketch of Quantum Computing
 Pratap Pattnaik (IBM, T. J. Watson Research Lab., USA)
10:30-11:00Coffee
11:00-12:30Discussion Session II: Memory in non conventional computing models
 Coordinators: D. Pleiter, J. Moreira
12:30-14:00Lunch (“Center Canteen”)
14:30-18:30Excursion to Rimini
19:30-22:00Social Dinner, Grand Hotel Cesenatico, Piazza Andrea Costa 1, 47042 Cesenatico (0547 80012).


Wednesday, September 20
07:30-08:45Breakfast (“Center Canteen”)
09:00-09:30Gluon: A Communication Framework for Distributed, Heterogeneous Graph Analytics
 Keshav Pingali (University of Texas at Austin, USA)
09:30-10:00A model-based approach to workload partitioning for heterogeneous systems
 Henk Sips (Delft Univ of Technology, Netherlands)
10:00-10:30On using data movement lower bounds to guide code optimization
 Saday Sadayappan (Ohio State University, USA)
10:30-11:00Coffee
11:00-11:30Towards multi-objective, region-based auto-tuning for parallel programs
 Thomas Fahringer (University of Innsbruck, Austria)
11:30-12:00Data transfer optimization for componentized computations in heterogeneous parallel systems using Smart Data-Containers
 Christoph Kessler (Linkoping University, Sweden)
12:00-12:30LAIK: A Library for Fault Tolerant Distribution of Global Data for Parallel Applications
 Josef Weidendorfer (T.U. Munich, Germany)
13:00-14:30Lunch (“Center Canteen”)
15:00-15:30On the use of Container Solutions for simplifying Simulation Environments
 Carsten Trinitis (T.U. Munich, Germany)
15:30-16:00Coffee
16:00-17:30Discussion Session III: Impact of memory and storage on architectural tradeoffs
 Coordinators: Arvind, C. Trinitis
18:15-18:30Bus Trip from Bertinoro to Forlimpopoli
18:30-19:30Visit Rocca di Forlimpopoli
20:00-22:00Dinner, Casa Artusi, Via A. Costa 27/31, 47034 Forlimpopoli (0543 748049).


Thursday, September 21
07:30-08:45Breakfast (“Center Canteen”)
09:00-09:30One-Sided Communication on a Non-Cache-Coherent Many-Core Architecture
 Steffen Christgau (University of Potsdam)
09:30-10:00I/O-Efficient Similarity Join
 Francesco Silvestri (University of Padova, Italy)
10:00-10:30Impact of memory data layouts on performance and energy-efficiency on state-of-the-art processors and accelerators
 Enrico Calore (University of Ferrara, Italy)
10:30-11:00Coffee
11:00-11:30Time complexity of scientific algorithms and memory access
 Thomas Husslein (Optware)
11:30-12:00Expected edit distance for random strings
 Michele Schimd (University of Padova, Italy)
12:00-13:30Discussion Session IV: Memory management (by OS, compilers, applications)
 Coordinators: S. Sadayappan, H. Sips
 Adjourn
13:30-14:30Lunch (“Center Canteen”)
19:30-21:30Dinner (“Center Canteen”)